Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a bit into, or reading a bit from, the SRAM cell.
With the increasing down-scaling of integrated circuits, the operation voltages of integrated circuits are reduced, including the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which are used to indicate how reliably the bits of the SRAM cells can be read from and written into, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.
Various approaches have been explored to lower VCCmin and to adjust for the ever-decreasing operation voltages. For example, dual-rail SRAM design uses a voltage regulator to provide a voltage, for example, higher than the operation voltage, to operate a memory. The regulated voltage is supplied to all of the macros in the memory. FIG. 1 illustrates a centralized scheme for supplying the regulated voltage (CVDD) to the memory. The memory, depending on its size, may have many macros including, for example, Macro1 through Macro8, as shown in FIG. 1. The voltage regulator may be placed at the center of the memory, and is connected to all of the macros through metal lines.
The centralized voltage supply scheme as shown in FIG. 1 suffers from drawbacks. First, the metal lines connected to the voltage regulator have voltage drops that can be represented as IR, wherein I is the current in the metal lines, and R is the line resistance, and the longer the metal lines are, the greater the voltage IR will be. Accordingly, the macros (such as macros Macro2, Macro3, Macro6, and Macro7) that are closer to the voltage regulator receive higher voltages (CVDD-I1R1) than the voltages (CVDD-I1R1-I2R2) received by the macros (such as macros Macro1, Macro4, Macro5, and Macro8) that are farther away from the voltage regulator. Second, with metal lines closer to the voltage regulator carrying higher currents than the metal lines farther away from the voltage regulator, current crowding may occur in the metal lines closer to the voltage regulator, and the Joule heating caused by the currents further results in an uneven temperature distribution. In addition, the centralized voltage regulator needs a customized compensation circuit to adjust its AC response. Since the required compensation circuit depends on the load size (the size of the memory), for each memory design, the respective compensation circuit has to be redesigned and tested.
Accordingly, what is needed in the art is a solution that may provide regulated voltages suited for the ever-decreasing operation voltages while at the same time overcoming the deficiencies of the prior art. In addition, the requirement for reducing VCCmin also needs to be addressed.